Reliable Power Aware ASICs

Highlights

  • What will you learn?

    1. Introduction to semi custom design flow: Introduction to
    semi-custom ASIC design flow, Challenges and
    opportunities, Need for semi-custom ASICS, Scope of semicustom ASICs, Industry Trends, Market reach and market
    share of semi-custom ASICs in VLSI (Very Large Scale
    Integrated Circuit) Industry, Overview of industry standard
    tools, Salient features of semi-custom ASICs, Levels of
    abstraction in VLSI designs, and Semi-custom oriented HDL
    coding
    2. Standard Cell Libraries for DSM: Different kinds of libraries
    and their relevance, Operating conditions, Wire-load
    models, Timing models, Timing arcs, Kinds of standard cells
    at 130nm, Cell attributes, Footprints, Naming conventions
    3. Timing Analysis in Digital Designs: Terminologies in timing
    analysis, Various kinds of timing paths, Properties of clock,
    Clock skew, Timing window and timing violations, Remedies
    for timing violations, Concept of slack, Critical path,
    Equations for timing calculations, Solving complex timing
    problems
    4. Synthesis and Constraints: Synthesis requirements,
    Synthesis process, Pareto points, Realization of constraints
    from specifications, Classes and significance of constraints,
    Environmental & optimization constraints, Design rule
    constraints, Timing and power constraints, Point-point
    exceptions, Chip level constraints, Case study — Complex
    sequential designs e.g., Systolic Array Multiplier
    5. Optimization & Low Power Techniques: Two level
    Optimization, Multi-Level optimization, Scheduling and
    allocation algorithms, Design abstraction levels,
    Representation domains, Control flow graph, Data flow
    graph, High level transformations, Low power techniques,
    Dynamic and leakage power optimization, Multi-VDD, Multi
    VTH, Retention registers, Top-down and bottom-up
    synthesis, Characterizing and propagating the constraints,
    80Hrs Rs.12000.00
    Register pipelining, Multi-Cycle paths, Case study -
    Communication block e.g., QAM
    6. Introduction to VLSI Testing: Need for testing, Importance
    of testing, Role of testing, Trends in testing, Test cost
    estimates, DFT cycle, Basic definitions like defect, fault and
    error, Testing at different levels, Difficulties and challenges
    of VLSI testing, VLSI chip yield, Fault coverage and defect
    level, Discussion of reliability issues, Basics of DFM
    7. Fault Modelling & Fault Simulation: Importance of fault
    modelling, Single stuck at fault, Multiple stuck at faults,
    Bridging faults, Pattern sensitive faults, Transistor faults,
    Cross point fault, Delay fault, Test and test set, Fault
    collapsing, Fault simulation concepts, Fault simulation
    approaches
    8. Design For Testability (DFT): DFT Introduction,
    Controllability, Observability, Need for DFT, DFT
    techniques, Adhoc DFT, Structured DFT, Scan based design,
    Scan flip-flop, Different scan types, Scan design rules, RTL
    for DFT, Test mode vs. Scan mode, DFT DRC rules, Scan clock
    skew, Multiple test insertion, Adding scan structure, Scan
    overheads, Testing scan registers — Case study
    Asynchronous FIFO/ NCO
    9. Static Timing Analysis (STA): Necessity of STA, Advanced
    timing analysis, Recovery time, Removal time, Importance
    and consequence of timing exceptions, False paths,
    Directed acyclic graphs, Bottleneck analysis, Case analysis,
    Mode analysis, Path groups, DFT aware timing schemes,
    Timing analysis of low power designs, On-Chip variation -
    Case study QAM / NCO
    10. Built In Self Test (BIST): BIST Architecture, Pseudo-Random
    generators, Signature analysis, Liner Feedback Shift
    Registers (LFSR) as pattern generators, LFSR as signature
    analyzers, Built In Logic Block Observers (BILBO)
    11. SYNOPSYS: Design Compiler, PrimeTime, Formality, DFT
    Compiler
    12. CADENCE: RTL Compiler

Details

What will you learn?

1. Introduction to semi custom design flow: Introduction to
semi-custom ASIC design flow, Challenges and
opportunities, Need for semi-custom ASICS, Scope of semicustom ASICs, Industry Trends, Market reach and market
share of semi-custom ASICs in VLSI (Very Large Scale
Integrated Circuit) Industry, Overview of industry standard
tools, Salient features of semi-custom ASICs, Levels of
abstraction in VLSI designs, and Semi-custom oriented HDL
coding
2. Standard Cell Libraries for DSM: Different kinds of libraries
and their relevance, Operating conditions, Wire-load
models, Timing models, Timing arcs, Kinds of standard cells
at 130nm, Cell attributes, Footprints, Naming conventions
3. Timing Analysis in Digital Designs: Terminologies in timing
analysis, Various kinds of timing paths, Properties of clock,
Clock skew, Timing window and timing violations, Remedies
for timing violations, Concept of slack, Critical path,
Equations for timing calculations, Solving complex timing
problems
4. Synthesis and Constraints: Synthesis requirements,
Synthesis process, Pareto points, Realization of constraints
from specifications, Classes and significance of constraints,
Environmental & optimization constraints, Design rule
constraints, Timing and power constraints, Point-point
exceptions, Chip level constraints, Case study — Complex
sequential designs e.g., Systolic Array Multiplier
5. Optimization & Low Power Techniques: Two level
Optimization, Multi-Level optimization, Scheduling and
allocation algorithms, Design abstraction levels,
Representation domains, Control flow graph, Data flow
graph, High level transformations, Low power techniques,
Dynamic and leakage power optimization, Multi-VDD, Multi
VTH, Retention registers, Top-down and bottom-up
synthesis, Characterizing and propagating the constraints,
80Hrs Rs.12000.00
Register pipelining, Multi-Cycle paths, Case study -
Communication block e.g., QAM
6. Introduction to VLSI Testing: Need for testing, Importance
of testing, Role of testing, Trends in testing, Test cost
estimates, DFT cycle, Basic definitions like defect, fault and
error, Testing at different levels, Difficulties and challenges
of VLSI testing, VLSI chip yield, Fault coverage and defect
level, Discussion of reliability issues, Basics of DFM
7. Fault Modelling & Fault Simulation: Importance of fault
modelling, Single stuck at fault, Multiple stuck at faults,
Bridging faults, Pattern sensitive faults, Transistor faults,
Cross point fault, Delay fault, Test and test set, Fault
collapsing, Fault simulation concepts, Fault simulation
approaches
8. Design For Testability (DFT): DFT Introduction,
Controllability, Observability, Need for DFT, DFT
techniques, Adhoc DFT, Structured DFT, Scan based design,
Scan flip-flop, Different scan types, Scan design rules, RTL
for DFT, Test mode vs. Scan mode, DFT DRC rules, Scan clock
skew, Multiple test insertion, Adding scan structure, Scan
overheads, Testing scan registers — Case study
Asynchronous FIFO/ NCO
9. Static Timing Analysis (STA): Necessity of STA, Advanced
timing analysis, Recovery time, Removal time, Importance
and consequence of timing exceptions, False paths,
Directed acyclic graphs, Bottleneck analysis, Case analysis,
Mode analysis, Path groups, DFT aware timing schemes,
Timing analysis of low power designs, On-Chip variation -
Case study QAM / NCO
10. Built In Self Test (BIST): BIST Architecture, Pseudo-Random
generators, Signature analysis, Liner Feedback Shift
Registers (LFSR) as pattern generators, LFSR as signature
analyzers, Built In Logic Block Observers (BILBO)
11. SYNOPSYS: Design Compiler, PrimeTime, Formality, DFT
Compiler
12. CADENCE: RTL Compiler

Batch Size

No Minimum

Course Material

Provided

Module Delivery

Fast Track — 4 Hrs / Day
Regular Track — 2 Hrs / Day

Duration

80 Hrs

Admissions

Eligibility

MTPs are open to engineering graduates/​diploma holders, engineering students and working professionals with an appropriate background.

Fees & Scholarships

₹12000

Contact
Email
email hidden; JavaScript is required