What will you learn?

1. Introduction to design verification: Need for verification,
verification process, challenges in verification, cost
involved, time involved, verification methodologies and
techniques, mission and goals of verification, verification
plans, verification flow, verification guidelines, HDL, HVL,
HDVL, System Verilog for design and verification,
verification methodology manual, industry standard
verification tools, Low power verification techniques.
2. Introduction to System Verilog: System Verilog
enhancements to Verilog 2001, Generations of System
Verilog standard and enhancements for hardware design,
System Verilog dot name and dot star enhancements, Case
study on instantiation example for complex ALU.
3. System Verilog verification features: Built- in data types,
new data types and operators, user defined types,
enumerated data types, System Verilog 2 state and 4 state
data types, static and automatic variables, verification
advantages of 2 state date types, synthesis guidelines,
structure declarations, assigning values, passing structures
through ports-synthesis guidelines, packed and unpacked
arrays, array of structures, unions and packed unions,
dynamic & associative arrays, Case study on verification of
memory.
4. System Verilog procedural blocks: System Verilog
specialised procedural blocks, latched procedural blocks,
sequential logic procedural blocks, synthesis guidelines,
task and function enhancements, passing task/​function
arguments by name. System Verilog procedural statements
for design verification. Enhanced for loops, do while loops,
continue and break, unique if else and priority if else,
modeling FSM with System Verilog, Case studies on
complex FSM implementations
5. Object Oriented Programming for verification: OOP
terminologies, local and global variables, scoping rules,
System Verilog’s class data type-defining class objects,
80Hrs Rs.12000.00
public Vs private, class methods-inheritance, single
inheritance, data hiding, building an object oriented test
bench, Case studies on OOP.
6. System Verilog assertions and interfaces: Assertions in
System Verilog, assertion concepts, immediate and
concurrent assertions, controlling assertion messages, case
studies on assertion based verification, System Verilog
interfaces, interface methods, verification with interfaces,
Case study on ATM router interface.
7. System Verilog randomization: Introduction, verification
strategy using VMM, constraint details, common
randomization problems, random control, random
generators, random device configuration, agent,
scoreboard, checker, driver, monitor and other functional
layers, building a complete verification environment, Case
study
8. SystemVerilog functional coverage: Introduction, coverage
types, functional coverage strategies, simple functional
coverage example, cover group, coverage options,
analyzing coverage data, measuring coverage statistics
during simulation, Case study on functional coverage
9. Advanced verification techniques: Save verification cycles,
bootstrapping the verification process, high-level modeling
concepts, coverage directed generation, verification
coverage, threads and mail boxes, program and clocking
blocks, active and reactive regions, interprocess
communication, advanced interfaces, Case study.
10. Tools Used: Synopsys and Cadence Tools, NCSIM,
ModelSim, VCS

Batch Size

No Minimum

Course Material

Provided

Module Delivery

Fast Track — 4 Hrs / Day
Regular Track — 2 Hrs / Day

Duration

80 Hrs