IC Planning and Implementation

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What will you learn?

  1. Introduction: Introduction to semi-custom ASIC flow, need and importance of physical design flow, overview of EDA tools for semi-custom IC design flow
  2. Data Preparation process: Introduction to data preparation functions performing essential tasks for cell libraries which includes creating cell libraries, importing cell data, translating and loading CLF timing data, specifying
    technology information, power and ground port types, optimizing the standard cell layout, extracting pin and
    blockage information, setting place and route boundaries and define wire tracks 80Hrs Rs.12000.00
  3. Chip input and output pads: Introduction to IO cells, types of analog and digital IO cells available in library physical
    specification of a standard IO cell, IO power and ground rail structure arrangement for regular and high tolerant IO cells , types of bond pad structures in the IO cell, simultaneous switching noise (SSN), Simultaneous switching output (SSO), driving index (DI) and factor (DF), concept and types of IO packaging, Flip chip IO cell and EM enhancement
  4. Floorplanning and implementation: Introduction to floor planning, differentiating between core limited and pad
    limited design flow, TDF/IO constraint files, defining best aspect ratio, core utilization, chip utilization, flat and
    hierarchical design flow, partitioning based on timing and interconnects information for hard macros, creating a physical layout.
  5. Power Planning and Management: Need for power management, core and IO level power estimation, limitation of core level and IO level power, top to bottom, bottom up approaches, estimating power budget for flattened and hierarchical designs, placement of power mesh (rectangular rings, straps, trunks) and power pads based on IR and EM based criteria
  6. Setup and Analyze Design Timing: Checking design data, loading timing constraints, setting up the environments for library, delay model, parasitics, optimizations, clock and net transition, maximum capacitance constraints on clock domains, TLU+ capacitance and resistance model, analyzing and probe timing paths 
  7. Placement and optimization: Introduction to placement, standard cell and macro/​DEF placement, timing driven and
    taming the congestion, detaching scan chains, location constraints, high fan-out net synthesis, placement
    optimization tasks, power optimization, area recovery 
  8. Clock Tree Synthesis (CTS): Introduction to CTS, physics of CTS, algorithms for CTS, single and distributed driver
    scheme, path length and its delay models for skew analysis, balanced clock tree, buffer insertion, constraints and device sizing under process variation in CTS, clock distribution network, low skew and power based global, local and useful skew analysis and optimization methodologies.
  9. Routing and Optimization techniques: Taxonomy of routing, routing algorithms, channel and switch box
    routing, balanced, and H tree clock routing, routing operations and optimization, density driven routing, post
    route optimization for timing, performing design finishing processes, optimizing yield, interactively cleaning up
    routing DRC, LVS check and errors, antenna checking and fixing violations, crosstalk prevention, analysis and fixing
  10. Design Signoff: Introduction to design signoff, data preparation flow for power sign off, checking Physical and
    logical connectivity power information, preparing data for hard/​soft macro extracting PG parasitics, performing power and rail analysis based on IR and EM criteria, performing design rule checking and connectivity verification,
    generating output for back annotation, performing various ECO analysis, industry standard GDII generation
  11. SYNOPSYS: Astro, Formality, PrimeTime, StarRC-XT, Jupiter XT, Hercules, IC Compiler
  12. CADENCE: SOC Encounter, First Encounter, FMS, Nanoroute, Voltage storm, Celtic IC

Batch Size

No Minimum

Course Material


Module Delivery

Fast Track — 4 Hrs / Day
Regular Track — 2 Hrs / Day


80 Hrs



MTPs are open to engineering graduates/​diploma holders, engineering students and working professionals with an appropriate background.

Application Process

Admission open around the year

Fees & Scholarships


Manager - Training
Murali R
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080 4906 5555