What will you learn?

1. Introduction: Introduction to VLSI systems, Introduction to reconfigurable systems, Need for reconfigurable systems, Introduction to design flow, Two competing implementation — ASIC & FPGA , Major FPGA vendors, The
   reconfigurable marketplace, PLD market share, Std Cell ASIC Development Cost Trend, Today’s typical design,
   Importance of reconfigurable systems in VLSI design, Application for reconfigurable systems, Future of reconfigurable systems, Introduction to FPGAs, Need of FPGAs in DSP Applications, DSP Processors vs. FPGAs,
   Product Roadmap, Review of PLA, PAL, Introduction to PLDs, Concept of CLB, Interconnect structure, ROM, PROM,
   Introduction to FPGA, FPGA vendors, FPGA structures 
2. RTL Coding for Synthesis: Introduction to RTL coding, Introduction to synthesis, Rules for combinational circuit’s
   synthesis, Avoiding unwanted latches, Rules for sequential circuit’s synthesis, Position dependent code, Resource
   sharing„ case, casex, casez etc.., Synthesizable and non synthesizable constructs, Case study – UART
3. Advanced Digital Design: Multipliers, Booth encoding scheme, Wallace tree, FIFO modelling, Finite state machines, FSM modelling in Verilog, Functions and Tasks, UDPs, Case study – FIFO
4. FPGA Architectures: XILINX FPGA Architectures, Anti-fuse and SRAMS, Logic elements and Look-up Tables, Dedicated multipliers, Reconfigurability, Distributed RAM, Shift registers, Digital Clock Managers, Macros, Spartan III and Virtex Architectures
5. FPGA Implementation: FPGA programming, Translate, Map, Floorplan, Place and Route, Post map and Post P&R
   simulation, UCF constraints, Manual mapping and placement, Reading and analysing reports-post synthesis,
   Post map simulation, Post P&R simulation, Configuring 80Hrs Rs.12000.00 FPGAs, FSM Extraction, Case study — Dual elevator controller
6. Constraints: Timing analysis, Area Constraints, Slack calculation, Data loss due to large skew, Maximum skew calculations with examples, Period constraints, OFFSET IN, OFFSET OUT Constraints, Multi cycle path, Timing
   constraints priority
7. FPGA Debugging and Advanced FPGA: Introduction to FPGA Debugging, Debugging using chip scope, Dual edge
   triggered FFs, Clock domains, Reset circuits, IP cores 
8. Tools Used: Xilinx ISE, ModelSim, ChipScopePro, System Generator

Batch Size

No Minimum

Course Material

Provided

Module Delivery

Fast Track — 4 Hrs / Day
Regular Track — 2 Hrs / Day

Duration

80 Hrs