What will you learn?

1. Full custom physical design: Introduction, challenges and

opportunities, nanometre designs, design flow, libraries,

technology files, tool set up, industry practices and CAD

tools. VLSI fabrication process and DSM/UDSM. Case study.

2. Layout introduction: Introduction, MOS transistor layers,

varies design styles, stick diagram, symbolic diagram,

design rules-lambda and micron rules 180nm, 90nm, 65nm,

45nm. Layout and physical verification, type’s full custom

layout — data path layout, custom digital layout, cell layout

and analog layout. Case study.

3. Digital layout design: Introduction, guide line of transistor

layout, pMOS and nMOS transistor layout, CMOS transistor

layout, sharing diffusion methods, optimization of

schematic diagram using dual graph methods and Euler’s

path. Combinational and sequential circuit layout, guard

ring protection for digital circuits. Case study.

4. Analog MOS circuits: Introduction, MOS Device

characterization, CMOS current mirrors, single stage

amplifier – common source amplifier, common drain

amplifier and common gate amplifier. Design of differential

amplifier and two stages CMOS Opamp. Design of resistors,

capacitors and inductors. Case study.

5. Analog layout design: Introduction, analog layout

techniques, multi finger, interdigitization, axis of symmetry,

common centroid, centroid of array, matched device

technique, dummy devices on surrounding. Passive

component layout — capacitor, resistor and inductor. Case

study.

6. Mixed signal layout issues: Introduction, floor planning of

analog and digital components, power supply and ground

pin issues, matching, shielding, interconnection issues. Case

study

80Hrs Rs.12000.00

7. Standard cell layout: Introduction, classification of STD cell,

standard cell design consideration, cell setting, STD cell

layout template creation. STD cell Performance for varies

process corners, Case study

8. Reliability issues: Introduction, electro migration, electro

migration reduction techniques, cross talk, effects of cross

talk, IR drop, antenna effect, hot electron effect, latch up

problem and latch up prevention. Case study

9. Nanometer design issues and Layout: Introduction, mask

error, optical proximities correction, phase shift masking,

resolution enhancement technique, gate oxide integrity,

metal erosion and metal over etching. Case study.

10. Tools used: Synopsys HSPICE , Cadence Virtuoso, MATLAB,

NanoSim, HSIM

Batch Size

No Minimum

Course Material

Provided

Module Delivery

Fast Track — 4 Hrs / Day
Regular Track — 2 Hrs / Day

Duration

80 Hrs